Reduce SOC debug task effort by 95%, go home at 5pm!

We did a quick comparison study of how long it took us to perform typical debug tasks; first, using just a waveform viewer and then, using our PDA protocol analysis tool along with a waveform viewer.

Just to be clear on terminology, a debug session (lets say, to debug a data mismatch) consists of multiple debug tasks (such as identifying or locating an AXI3 write transaction, checking the length of a data payload etc). Each debug task might require multiple steps. For example, a simple debug task such as finding an AXI3 write transaction’s Address, data and response phase might require following steps to be performed on a waveform viewer:

1. Find the relevant signals in the RTL hierarchy

2. Add them to the waveform

3. Scroll to the correct timestamp

4. Zoom in/out to show the correct time range

5. Rearrange the signals to show all relevant signals together

6. Open relevant spec and scroll down to the relevant section and lookup how the WID is related to AWID and BID

7. Find out which data and response phase corresponds to the AXI3 write transaction (Not easy because of pipelining and also because data phase can occur before address phase)

Typically an experienced engineer might take 5 minutes, whereas a new college grad can take more than 15-20 minutes, for this very basic debug task!

Phew! No wonder that today debug is a major component of design verification:


In comparison, the same task can be done under 10 seconds when using our PDA soft protocol analyzer along with a waveform viewer. How is this possible, you ask? Here is how:

1. The PDA tool processes signal dumps and shows PACKETs and TRANSACTIONs instead of low level interface signals

2. It takes less than 10 seconds to find the AXI3 write transaction using the PDAs spread-sheet like filter and search features

3. the PDA automatically loads the relevant signals into your waveform viewer if you want to look at signal level details. You don’t have to browse through deep RTL hierarchies to find them!!

4. The PDA tool understands the protocol and hence is able to find all the phases of a transaction and mark them out for you. No need to hand decode a transaction, the PDA tool shows whether the transaction is a WRITE or a READ, its Size and Burst length, its Memory Type and Lock Type in english words and not cryptic binary values.

Please have a look at a short 3 minute video (No earphones? No worries! It has subtitles!) on how PDA works with a waveform viewer.

Here are a few other representative debug tasks that we compared:

Simple Debug Steps Waveform (only) Time PDA Time Effort Reduction
Decoding a USB3 DPH packet


  1. Thinking effort/time:
    1. Referring to the spec to get the packet structure may take 2-5 mins
    2. Identifying what needs to be done in waveform viewer may take 1-2 min
  2. Tool effort/time: finding the first DP in the waveform and actually decoding the DPH fields will take another 5 mins. Scrambling of data would also complicate the decode.


  1. Thinking effort/time: Low effort since tool software presents decoded data
  2. Tool effort/time: All we need to do is filter the ‘Type’ column to show DPH only and we can see all the decoded fields in their respective columns
8-11 mins 10 sec ~97%
Counting number of USB3 Data packets


  1. Thinking effort/time:
    1. Referring to the spec to identify framing symbol bit-pattern will take another 1-2 mins
    2. Formulating a logical expression in the waveform viewer to get all DPs, this may take 2-3 mins
  2. Tool effort/time: Traversing through the waveform and counting the DPs might take a lot of time depending on the number of DPs. For a simple example it took 2 min 18 sec


  1. Tool effort/time: Filter by DPH and scroll down to the end to check the number of DPHs , alternatively make use of DPHDPP stats app to get the number of DPHs and DPPs.
6+ mins 20 sec ~94%
Identify all phases of an AXI3 Write transaction


  1. Tool effort/time: To find the phases that constitutes an AXI3 transaction we need to match the WIDs with AWIDs and BIDs (for write transaction). This becomes more difficult when there is deep pipelining and IDs are same for all transactions.


  1. Tool effort/time: Hierarchical view directly clubs the address, data and response phases together for a transaction.
5+ mins 10 sec ~96%
Perform protocol level diff of USB3 packets


  1. Thinking effort/time: To come up with an algorithm for performing protocol level diff will be very time consuming.
  2. Tool effort/time: This debug step can’t be done in the waveform viewer directly. Packets will have to be extracted manually, logged into a file and then compared with a diff tool.


  1. Thinking effort/time: Need to identify the endpoint number and direction that we want to compare between reference and current signal dump files
  2. Tool effort/time: PDA supports diff feature directly

Timing results are obtained by using diff on our example for BULK IN endpoint type.

45+ mins 50 sec ~99%
Find contents of memory/register inside an address range at any given time


  1. Tool effort time: We need to search for all memory accesses inside the address range and log the contents till a particular time. This can be very time consuming.


  1. Tool effort/time: supports a memory view feature which shows all the memory address contents with time.
30+ mins 10 sec ~99%
Find how a USB3 transfer is broken into USB3 packets


  1. Tool effort/time: We need to look for a packets belonging to a particular endpoint address and try to figure out where did the transfer start and end. This can’t be done easily in a waveform viewer for large transfers. Scrambling of data would also complicate the decode.


  1. Tool effort/time: PDA’s hierarchical view displays how a USB3 transfer is broken into packets

These numbers are for a BULK IN transfer.

30+ mins 40 sec ~97%
Find last data written to a particular address on DDR2


  1. Thinking effort/time:
    1. Referring to Spec to identify address decode, command decode and command sequence will take ~7-8 mins.
    2. We need to use the address signals to get the bank and row address for the Activate command and column address during Write.  (5-8 mins)
  2. Tool effort/time: Create a logical expression for marking the correct transaction’s address/command phase, followed by looking at the waveform to identify the last access and its corresponding data phase. (may take more than 2 mins to get to the last write data value)


  1. Tool effort/time: We just need to look for last write command for given address. This can be done by column filtering on CMD type (Read / Write ) along with Address.
10 mins 20 sec ~96%
Match a USB3 DP with its TP


  1. Tool effort/time: To match a Setup DPH with a TP looking at their endpoint and  sequence numbers: This will require decoding of endpoint and sequence number fields in DP and TP packets. Additional complication arises if there are flow control packets (NRDY/ERDY) exchanged or if the DP is retried at protocol level.


  1. Tool effort/time: PDA has an application to match DP with ACK TP can be used to do this quickly for all DPH.
10+ mins 20 sec ~96%
Count number of Read transactions seen on an AXI3 interface


  1. Tool effort/time: Create a logical expression that asserts to 1 whenever there is a valid address phase on the AXI3 interface. Count the number of clock cycles during which this logical expression is asserted.


  1. Tool effort/time: Filter the AXI3 transactions table to show only Read transactions
5 mins 10 sec ~96%
Find the number of IN transfers for each endpoint in USB3


  1. Tool effort/time: This can’t be done manually using waveform viewer for large number of transfers.


  1. Tool effort/time: Filter the table for USB3 transfers to show only IN transfers for a particular endpoint number. The number of rows in the filtered table is equal to number of transfers for that endpoint.
 very large 19 sec 100%


During a typical debug session, an engineer will perform multiple debug tasks to establish or eliminate the various hypothesis that he might come up with. With the PDA tool, engineers have all the relevant data and facts at their fingertips. With time saved on multiple debug tasks, the overall debug effort is reduced.

Want to get back home by 5 PM instead of wasting your life in front of waveforms? You should contact us! If these numbers sound too good, you should request for an evaluation!


Aditya Mittal

Bhavesh Shrivastava

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