Debugging AXI3: Waveform + Protocol Analyzer

We have all debugged SOC and IP level issues using signal level waveforms. It’s a tedious and laborious process. Are there any ways that can make design debug easier? Wouldn’t it be great if I could look at fully decoded packets and transactions instead of signal toggles? In this series of posts, we will try to come up with the best way to look at some typical interfaces in order to reduce debug effort and increase productivity.

AXI3

AXI3 is a system bus that offers a high speed inter-connect between subsystems of an SOC. Some of the features include:

Separate Address, Control and Data Phases
Burst Transactions
Multiple outstanding addresses
Out of order completion

Because the bus is pipelined (multiple phases) and completions/responses can come out of order, it is difficult to make sense of the bus activity when one looks at the signal level details. I have to track all the incomplete phases of every outstanding AXI transaction. Do I really need to do this? Is this not something machines should be doing for me? After all, computers are good at these kind of mundane things. Once I get the right information, I can use my creativity to find design problems or develop insights, which is what a human is good at!

The following waveform show an AXI write where the data phase occurs before the address phase. If the same information is presented as a list of transactions, where each line in the list shows all the attributes of the transaction, one can make sense much more easily. I don’t have to manually figure out the address phase corresponding to the current data phase. The address phase might have occurred a number of clock cycles earlier OR even later than the data phase!

So how can you get AXI3 transactions from signal level details? The PDA tool from Arrow Devices can help you. You can also look at a short 3 minute video. (No earphones? No worries! It has subtitles!)

When used along with a traditional waveform viewer, the PDA tool provides excellent debug visibility and traceability; from signal level to transaction level.

Author: Aditya Mittal

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