Debugging PCIe: Using a Simulation Protocol Analyzer for faster debug!

We have all debugged SOC and IP level issues using signal level waveforms. Its a tedious and laborious process. Are there any ways that can make design debug easier? Wouldn’t it be great if I could look at fully decoded transactions instead of signal toggles? In this series of posts, we will try to come up with the best way to look at some typical interfaces in order to reduce debug effort and increase productivity.


PCIe (Peripheral Component Interconnect Express) is the interconnect of choice for providing a high bandiwth, low latency interconnect between system memory and peripherals. PCIe has successfully replaced the old PCI and PCI-X specifications. Wheras PCI used a shared, parallel bus architecture, PCIe uses a point-to-point, serial bus architecure. At the protocol level, PCIe communication occurs in the form of packets exchanged over the serial interconnect.

At the physical level, a PCIe link consists from one to 32 lanes, each operating at 2.5 GHz (gen 1), 5.0 GHz (gen 2) or 8 GHz (gen 3). At these high clock speeds, data has to be encoded (8b/10b for gen 1 and gen 2, 128b/130b for gen 3) appropiately in order to allow reliable clock recovery on the receiver side. Data might also be “scrambled” in order to reduce EMI interference.

The serial nature of the bus, encoding and scrambling makes it virtually impossible to make sense of what is going on on the bus, by just looking at the waveform.

Wouldnt it be wonderful if you could see the various packets being exchanged on the PCIe link in a spreadsheet like format that you could filter and search through? This is what our PDA tool does. It reads signal dumps, decodes the PCIe packets by looking at signal toggles on the PCIe link and reports these in a user friendly GUI. (quick 3-min demo video here)

In the below screenshot, our PDA tool shows some of the Link level packets on a PCIe gen 2 system. Additionally, the tool has also inferred PCIe Transactions by parsing through PCIe packets and grouping packets that make up a single PCIe transaction. This allows you to correlate PCIe transactions traffic with the high level test intent.


As you can see, the PDA tool provides you with a precise summary of information extracted from your signal dump file. You do not have to struggle with remembering the bus encoding (Eg: What is the format of a Transaction Packet?). The tool does all that for you. It even takes care of the pipelined nature of the bus and reports transaction information in a one-line summary! How easy is that!

This is especially useful for engineers debugging at system level and who might not be well aware of the intricacies of the PCIe protocol. Using the PDA tool, even inexperienced engineers can debug transactions through the PCIe interface and thus improve their debug productivity.

When used along with a traditional waveform viewer, the PDA tool provides excellent debug visibility and traceability; from signal level to transaction level.

The PDA tool from Arrow Devices can help you. You can also look at a short 3 minute video. (No earphones? No worries! It has subtitles!)

[update] PDA is better than a VIP monitor because:

1. It analyzes signal dumps, so the data presented is more accurate and correlatable with waveforms. No changes are required in the verification environment to get this debug information
2. It can report transaction level activity on internal interfaces which are not driven by a VIP (RTL to RTL interfaces)
3. The GUI allows capability to filter, search and even perform DIFF. All these analysis features are protocol aware
4. The tool provides data in a form that allows engineers to automate analysis and debug tasks using simple Python scripts. This is difficult with text log files dumped by monitors
5. Since this tool analyzes signal activity, it works equally well for Emulation. For example, it can analyze DDR signals from an emulation run to extract DDR transactions
6. The tool provides a “memory view” that allows you to examine the data stored in the DDR memory at any given timestamp

If you want to make design debug easy, contact us using the button below!

Author: Aditya Mittal

Leave a Reply

Fill in your details below or click an icon to log in: Logo

You are commenting using your account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s