Have you ever wondered how you can substantially reduce your debug effort for today’s complex SOC chip designs?
Designs today employ multiple complex interface protocols such as USB, DDR, PCIE, UFS etc and employ internal bus protocols such as AXI, AHB, APB, PLB etc. Today, SOC development require engineers to understand multiple of these protocols for even simple debug tasks. For example, a system level verification engineer would need to know AXI and APB protocols to understand which kind of transaction the system software is trying to initiate on the system bus. She would also need to know protocols such as Ethernet, PCIE and/or USB to make sense of bus transactions on chip interfaces.
These protocols are complicated to say the least. Their specification documents run over hundreds of pages. Many of these protocols support features such as out-of-order completions, parallelism between threads etc. These kind of features make it harder to make sense of waveforms.
The PDA tool eliminates this complexity by providing the debug engineer with easy to understand debug information. The PDA tool processes the signal level data, decodes packets, transactions and transfers from the signal level data and presents this to the debug engineer. The PDA output is so intuitive and easy to understand the the debug engineer can quickly narrow down to the bug.
What earlier required in depth knowledge of multiple specifications can now be achieved by common sense.
Here is a short document that compares debug times measured for some simple debug tasks, with and without the PDA tool: