With every generation, chips have become more complex and transistor counts have increased exponentially (according to the famous Moore’s Law). This exponential growth in complexity and size has led to a corresponding growth in EDA tool data-base sizes (HDL files, simulation logs, waveform dumps, net-lists, timing reports, GDSII etc) as well as compute power required … Continue reading Is it possible to develop high performance tools in Python?
Have you ever wondered how you can substantially reduce your debug effort for today's complex SOC chip designs? Designs today employ multiple complex interface protocols such as USB, DDR, PCIE, UFS etc and employ internal bus protocols such as AXI, AHB, APB, PLB etc. Today, SOC development require engineers to understand multiple of these protocols … Continue reading Debug Breakthrough: PDA gives 10x improvement for debug tasks
We present you with a few cheat-sheets that can help you design, verify and debug FASTER! These cheat-sheets contain condensed spec details and information that you will need to refer frequently. This gift is SHARABLE! Please FORWARD and SHARE on LinkedIn with friends and colleagues! USB 3.1 - Download USB 3.0 - Download PCIE3 - Download PCIE2 - Download … Continue reading 9 interface protocol cheat-sheets to make your Design/Verif/Debug tasks easy!
Please raise your hand, if you have ever felt like putting a fork in your left eye due to debugging issues. Below is an attempt to ensure that feeling never comes back, and pave way for you to become a Debug Ninja! So Why Is Mastering Debugging Important Today? In earlier times, debugging was something … Continue reading How to become a Debug Ninja!
This is a detailed technical comparison between USB 3.1 & USB 3.0 specifications. Its my endevour to help you in quickly figuring out the spec updates that matter most! But First, A Brief Recap of the USB Journey Initially, USB had two speed options - 12 Mbps and 1.5 Mbps. In the year 2000, USB … Continue reading USB 3.1 vs USB 3.0: Technical Comparison
If you are new to the world of design and verification, you probably have a LOT of questions! One of them may pertain to an important element – the Clock Data Recovery. In this blog, we try and de-mystify this process. The purpose of designing various protocols is to transfer a set of information (data) … Continue reading Beginners Guide To Clock Data Recovery
With increasing complexity in today’s SoC designs, logic verification is one hurdle that all designers are eager to overcome. A majority of the verification effort is spent on debug. This is because typical SoCs consist of a variety of IPs and interfaces. In cases where data has to flow through multiple interfaces in order to … Continue reading SoC Debug Made Easy!
In this blog, we will look at the Protocol Debug Analyzer (PDA) tool can analyze Signal Dump files and provide transaction and other higher abstraction views. We will explore how the tool augments your Waveform viewer, allowing you to drill down from transaction to signal level details and vice-versa. We will use an example Signal Dump … Continue reading How to make your Waveform viewer SMART!
Ok, so I ran my regression tests after making a few minor RTL changes and guess what?! Some tests failed! They were passing and now they fail! Aargh! Wish I had a quick way to compare the passing and failing runs… We have all experienced this situation where we want to debug by comparison. Performing … Continue reading How to do a Protocol level Diff/Compare
We have all debugged SOC and IP level issues using signal level waveforms. It's a tedious and laborious process. Are there any ways that can make design debug easier? Wouldn't it be great if I could look at fully decoded packets and transactions instead of signal toggles? In this series of posts, we will try … Continue reading Debugging AXI3: Waveform + Protocol Analyzer