Debugging USB3: Waveform + Protocol Analyzer

We have all debugged SOC and IP level issues using signal level waveforms. Its a tedious and laborious process. Are there any ways that can make design debug easier? Wouldn't it be great if I could look at fully decoded packets and transactions instead of signal toggles? In this series of posts, we will try … Continue reading Debugging USB3: Waveform + Protocol Analyzer

Debugging DDRn: Waveform + Protocol Analyzer

We have all debugged SOC and IP level issues using signal level waveforms. Its a tedious and laborious process. Are there any ways that can make design debug easier? Wouldn't it be great if I could look at fully decoded transactions instead of signal toggles? In this series of posts, we will try to come up with … Continue reading Debugging DDRn: Waveform + Protocol Analyzer

Debugging PCIe: Using a Simulation Protocol Analyzer for faster debug!

We have all debugged SOC and IP level issues using signal level waveforms. Its a tedious and laborious process. Are there any ways that can make design debug easier? Wouldn't it be great if I could look at fully decoded transactions instead of signal toggles? In this series of posts, we will try to come up with … Continue reading Debugging PCIe: Using a Simulation Protocol Analyzer for faster debug!

Debugging CSI-2: Waveform + Protocol Analyzer = Happiness!

We have all debugged SOC and IP level issues using signal level waveforms. Its a tedious and laborious process. Are there any ways that can make design debug easier? Wouldn't it be great if I could look at fully decoded transactions instead of signal toggles? In this series of posts, we will try to come up with … Continue reading Debugging CSI-2: Waveform + Protocol Analyzer = Happiness!